xilinx vs altera fpga which one is better
I'm very new to programmable logic world and have never worked with any HDL languages, but I certainly want to get started with FPGA. At the moment the goal is to develop/simulate simple 8bit CPU and maybe (in the future) do some graphic output. As I understand there are two big players in the FPGA market: Xilinx and Altera. I have very though budget - 40$. Also, I'm a little bit confused of capabilities that varies from board to board (regardless of vendor). For example, some of the boards - even based on the same chip - has VGA port (or COM/RS-232 port), RJ-45 socket and even audio line out/in; some of them just have an array of pins (if so does it mean that FPGA has Digital/Analog I/O? ).
So I'm curious if it will be possible to "extend" capabilities (eg add D-sub port to output some graphics or phone socket for audio) on the board that doesn't have a required interface. I need an advice and certainly some explanation what the board better to buy in my "noob" case. I use aliexpress to buy such a things, so here are some examples I've found "appeal":
I have a Verilog design which I compiled on both Xilinx ISE and Altera's Quartus II. Both are the Web versions.
The design has a lot of 32-bit registers being used as shift registers and accumulators. There's a fair amount of adders and combinational logic thrown in there as well. The design compiles on both platforms without any errors and only a couple of warnings about unused inputs (nothing that should affect the implementation though). However, the amount of real estate the design takes up is grossly different. Here's what Altera produced: Total logic elements 39,989 / 55,856 ( 72 % ) Total combinational functions 28,946 / 55,856 ( 52 % ) Dedicated logic registers 22,281 / 55,856 ( 40 % ) Total memory bits 13,024 / 2,396,160 ( 1 % ) I let Quartus choose the device and it chose the 55K element chip.
As can be seen, the design fits easily with room to spare. Now here's the result from ISE (14. 5) for the 75K element Spartan-6 device: Found area constraint ratio of 100 (+ 5) on block testdesign, actual ratio is 149. WARNING:Xst:2254 - Area constraint could not be met for block testdesign, final ratio is 146.
If I understand this, both platforms used roughly the same amount of logic elements and registers for the design solution, but for some reason the Xilinx device is unable to hold the design despite being a significantly larger chip. I'm hoping I'm just not understanding what ISE is telling me or that I have an option turned on/off that is causing implementation issues. (ISE is set to use the area strategy. ) I would really like to use the Xilinx device for this for a variety of reasons. Any ideas?
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